Mesh Architecture For Processor Chips
by
Randy Mears
When it comes to modern processor chips, multicore chips are in. First there were dual cores, then quads and I guess they will keep doubling until they reach the point of diminishing returns. According to this article about a new mesh architecture for multicore chips; the central bus architecture around which current multicore chips are built will hit the point of diminishing returns at 16 cores on a single chip. It appears that the current architecture simply won’t scale. With the industry hoping to double cores per chip every 18 months, and given that quads are already out there, that gives us just one more generation before we hit the wall. As indicated in the above link, Tilera appears to be the first company to ship a mesh architecture multicore chip. With 64 processors it leisurely cruises past the 16 processor central bus wall mentioned above.
When it comes to fabricating massively multicore chips the idea of a mesh architecture isn’t new. Intel even has a mesh based 80-core prototype; one that’s been in the news since February. If only software were as far along as processor hardware, maybe we could actually take advantage of all this massive parallelism. Tilera does recognize the barriers that today’s software design, techniques and tools present for massively parallel computers and takes measures to address those issues for its customers but as we move into more and more parallelism, particularly on personal computers, don’t we need to find a whole new approach to software design and development? Or will the decades of legacy software continue to hold us back?
All the attention to software, as it relates to massive parallelism, is interesting but not new, or breakthrough. While we can certainly benefit from increasing processor cores and slicing and dicing problems into sub-problems (from a software development standpoint), the real leap will come when we have a novel approach to software design and development that lets the developer focus on the problem at hand and not the nuances of engaging parallel processors to solve it.
